Seamless clock

ABSTRACT

System ( 10 ) comprising at least two units ( 1, 2 ) with clock functionality, the units being coupled to a common system clock line (SCLK), a common internal clock line (ICLK), and a logic bus (L-BUS), whereby one sole unit ( 1, 2 ) is being dedicated as a mater unit at a time. One source clock signal (CLK 10,  CLK 20 ) of a unit is output on the internal clock line (ICLK) and all PLL devices of all units generates PLL output signals derived from the internal clock signal, the outputs of the PLL devices (CLKP 1,  CLKP 2 ) being in phase with one another such that switchover from one PLL output signal to another is seamless.

FIELD OF THE INVENTION

The present invention relates to systems relying on a plurality of clocksources.

BACKGROUND OF THE INVENTION

Larger computer and control systems are often distributed on a pluralityof circuit boards, each having its own clock source. Typically, realtime applications require accurate phase aligned reference clock signalsin order to guarantee that the operation will be unaffected in case of afailure of a clock source or failure of a unit incorporating such aclock source. It is known to generate a common system clock from atleast one of a plurality of clock sources, such that a system referenceclock signal is provided, preferably with insignificant phase delays, toeach of the plurality of boards. Should any circuit board or any clocksource malfunction, the function of the system clock should be restoredor retained. It should also be possible to replace a single circuitboard without seriously interrupting the operation of the remainingsystem, i.e. hot swapping circuit boards.

Prior art document U.S. Pat. No. 6,194,969 shows a redundant clocksystem comprising a first clock board and a second clock board, a systemboard and a system controller. Each clock board comprises at least oneclock source. In operation, one clock board is providing a master clocksignal while the other is providing a slave aligned clock signal. If themaster clock signal is found to loose as little as one clock edge, aninput clock failure is identified by the system board and a switchoveris made, for instance within three clock cycles, to the redundant slaveclock signal in phase alignment with the master clock signal. Any of thefirst or second clock boards may be hot swapped with a third clockboard.

In prior art document U.S. Pat. No. 6,194,969 two phase-locked signalsare provided for redundancy. To make use of these redundant clocksignals, every receiver needs two inputs and selection circuitry toswitch between the redundant clock signals.

Prior art document U.S. Pat. No. 4,282,493 shows a redundant clockgenerating circuitry for providing an uninterrupted clock signal. Twoclock modules are provided each comprising a first PLL oscillator and asecond PLL oscillator monitoring the first PLL oscillator and providingan out-of-lock signal upon detection of any disparity there-between. Oneclock is master and the other is slave. Switching the master from oneclock module to the other will not cause any phase discontinuities ormomentary bit transitions on output clock signals because the master andslave clock are phase locked with regard to one another prior to andafter switching. Switching from one clock to the other may be initiatedupon detection of a malfunction as indicated by an out-of-lock signal.

If there is a failure on the master clock module in U.S. Pat. No.4,282,493, the signal from the slave unit will seamlessly take over.However, when the slave module takes over as master, the signal fromthis board is physically driven through the board of the previousmaster. If the previous master board is removed, all boards of thesystem will loose their clock signal; i.e. hot-swapping of the clockmodules is not possible.

Moreover, apart from the PLL devices used for phase locking of the twosources, U.S. Pat. No. 4,282,493 assumes a PLL in the receiver end andrequires additional logic on all boards of the system sharing a commonclock in the same manner as in U.S. Pat. No. 6,194,969.

SUMMARY OF THE INVENTION

It is a primary object of the invention to set forth a system, whichprovides a virtually seamless clock signal if a local clock or clockunit malfunctions or a clock unit is hot swapped and which does notrequire a superior system component to secure redundancy.

This object has been accomplished by the subject matter defined by claim1.

It is moreover an object to set forth an extendable clock system, whichis based on a single modular unit.

This object has been accomplished by claim 2.

It is a further object of the invention to set forth a unit whichprovides a virtually seamless clock signal if a local clock or clockunit malfunctions or a clock unit is hot swapped and which does notrequire a superior system component to secure redundancy.

This object has been accomplished by the subject matter set forth inclaim 8.

More advantages will appear from the following detailed description ofpreferred embodiments of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a preferred embodiment of the invention of local clockcircuitry of two exemplary units being interconnected by means of aclock bus and logic bus,

FIG. 2 shows an exemplary embodiment comprising three redundant clockboards and two boards with additional functionality but without anyclock circuitry.

FIG. 3 shows an exemplary timing diagram relating to the operation ofthe units shown in FIG. 1, in which initially unit 1 is master and unit2 is slave and where subsequently unit 2 is master and unit 1 is slave,and

FIG. 4 shows a preferred embodiment of fault sense circuitry in thefirst unit shown in FIG. 1.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS OF THE INVENTION

In FIG. 1, an apparatus 10 comprising two units 1 and 2 have beendisclosed. Each unit comprises a clock functionality and additionalfunctionality (not shown). The clock functionality of the two units areidentical and are coupled to one another over a clock bus, comprising asystem clock line, SCLK, and an internal clock line, ICLK, and over alogic bus, L-BUS. The additional functionality could relate to virtuallyany functionality requiring a clock signal, such as telecom radio basestation functionality. The additional functionality of the units may notnecessarily be the same. Advantageously, the units could be arranged onseparate circuit boards fitting in a common rack. Moreover, three ormore units could be coupled to the above-mentioned busses; whereby agiven unit is master and the other units are slaves. The system clockSCLK is the clock reference signal provided to all units from the givendedicated master unit.

The first unit comprises a logic section MS1, a clock source CLK1,comprising for instance a quartz clock, a phase lock loop (PLL) deviceP1, a first bidirectional port BD11 and a second bi-directional portBD12.

The clock source CLK1 is generating a clock source signal CLK10, whichmay be halted upon reception of an asynchronous command signal ASCMD1.The clock source signal CLK10 is issued to the first bi-directional portBD11. Depending on the state of an enable signal BD11E, BD11 has thefollowing function: If enabled, BD11 outputs the source clock signalCLK10 to the internal clock ICLK over a line B11 and concurrentlyimports the same clock signal. If disabled, BD11 imports a clock signalfrom the internal clock ICLK over a line B11

The first bi-directional port BD11 transfers the occurring source signalon line B11 into line CLKB1 to phased lock loop (PLL) device P1. As iscommonly known, a PLL device will, if exposed to a periodical inputsignal, provide the same signal on its output. However, should a singlepulse alter in the input signal or should the frequency of the inputsignal alter stepwise, the PLL will—in analogy to a gyro system—slowlychange its output such that the output gradually will match thefrequency and phase of the incoming signal. The PLL device contains aninternal feedback loop illustrated by line P1L.

The PLL device P1 produces a derived clock signal CLKP1 that is input tosecond bi-directional port BD12. Depending on the state of an enablesignal BD12E, BD12 has the following function: If enabled, BD12 outputsthe source clock signal CLKP1 to the system clock SCLK over a line B12and concurrently imports the same clock signal. If disabled, BD12imports a clock signal from the system clock SCLK over a line B12 andpasses it further on as a signal CLKL1.

The derived clock signal present on system clock SCLK is lead to logicsection MS1.

Both enable signals BD11E and BD12E is output from logic signal MS1.

The second unit 2 is identical to unit 1, although the referencenumerals of unit 2 are different for the same type of elements found inunit 1.

As mentioned above, operation is so that one unit is master while theremaining units are slaves. In a preferred embodiment, the master unitcontrols the system clock SCLK and the internal clock ICLK, while theslave units sense the former two clock signals.

The change of master from one unit to another is accomplished accordingto the operation of logic sections MS1 and MS2. The operation enablesswitching according to sensed error states but also enables intendedmaster changeovers, which are not caused by faults. The dedication ofmaster unit is dependent on a signal being given on the L-bus so as notto select a given unit for being a master unit, and if a given unit isdedicated as master unit when such a signal on the L-bus is given, thesystem performs a switchover causing another unit as the one notselected to be dedicated as master unit.

The changeover could be effectuated by an external asynchronous signal,such as the one given when an operator prepares for a hot swap and forinstance gives a command signal ASCMP1.

The logic section of a given unit is synchronised with the system clockSCLK over the signal lines CLKL1, CLKL2.

In FIG. 2, another exemplary coupling scheme according to the inventionhas been shown comprising three redundant clock units 1, 2 and 3 onseparate boards and two boards 6, 7 with additional functionality butwithout any clock generating or clock evaluating functionality. Allboards are connected over the system clock line SCLK. The clock unit 3and additional functionality 5 reside on the same board. The clock unitsare moreover interconnected by the L-BUS and the internal clock lineICLK.

The operation shall now be explained with regard to the followingexemplary timing diagram shown in FIG. 3, in which an externalasynchronous input effects a switchover.

At a given point in time T1, the two clock sources CLK1 and CLK2 producetwo signals CLK10 and CLK20 of substantially the same frequency butwhich are lagging in phase to one another with an arbitrary phasedifference that could amount to ±180 degrees.

As appears from FIG. 3, at time T1 the internal clock ICLK is in phasewith the system clock SCLK.

At time T2, a signal indicative of an intended change in master fromunit 1 to unit 2 is signalled on the L-BUS. Following the subsequentpositive flank T3 of the system clock SCLK, all enable signals BD11 E,BD12E, BD21E and BD22E changes states at T4. This effects the change ofmaster from unit 1 to unit 2.

The internal clock signal ICLK is given by the source clock chosen,corresponding to the selected master. Before T5, the internal clock isfollowing CLK10 and after T5, the internal clock follows CLK20, assignalled over BD11E and BD21E.

As is seen from FIG. 3, a phase shift in ICLK occurs at T5 as switchoveris made between CLK1O and CLK20.

The signalling from the logic sections MS1 and MS2 secures that at alltimes the signals CLKB1, CLKB2 are fetched from the same clock source.Hence, the internal clock ICLK always depends on the one selectedinternal clock. Consequently, the inputs to the various PLL's areidentical. All PLL's have the same predetermined characteristic and thetolerance level applicable for the PLL units are chosen to beappropriately small. Hence, the various outputs of the PLL's—CLKP1 andCLKP2—will always be substantially in phase and be dependent on theprevalent dedicated internal clock signal ICLK. Therefore, the systemclock SCLK can be switched over virtually seamlessly from CLKP1 to CLKP2and vice versa as controlled by logic signals BD12E and BD22E. The PLL'sP1 and P2 will maintain generating phase aligned clock signals CLKP1 andCLKP2 for several clock cycles, even if no internal clock ICLK signal ispresent.

When the ICLK signal changes abruptly from a first phase value to asecond phase value—as illustrated at T5—the PLL's will gradually changethe phase of their outputs so that after a given period—at T6—the PLL'swill be in phase with the second phase value of the ICLK signal. Theinertia of the PLL's and the corresponding period of “ramp alignment” ischosen to match the system clock requirements of the additionalfunctionality mentioned above. The phase change is off course associatedwith a change in clock cycle frequency. In FIG. 3, the frequency FSC ofthe system clock signal SCLK has been illustrated as changing from afirst frequency F1 at time T1 to a second frequency F2 immediately afterT5. Subsequently, the frequency FSC approaches asymptotically the firstfrequency F1. Advantageously, the alignment period T5-T6 is chosen toseveral clock cycles, such that the additional functionality “won'tnotice” the phase change. At time T6, the phase difference isillustrated as being insignificant.

As explained above, the enable signals BD11E, BD12E, BD21E and BD22E arerelated to the first positive edge of SCLK that is overlapped by theL-bus signal. Thereby the state changes of enable signals occurfollowing a positive edge of SCLK. The short delay from SCLK going highat T3 to the enable signals are changing state at T4 is due topropagation delays in the circuitry.

Consequently, the switching of output enable signals is firstaccomplished when it is known that SCLK is in a logic high state at atime with a certain predetermined security time interval from statechanges, i.e. at a certain distance to the flanks. It is important thatthe switch does not occur when there is a transition of SCLK, since thiscould cause disturbances at the receiver end.

An external circuitry is used to bias the SCLK line to a logic highstate, in case no unit should drive the SCLK line. Since switching canonly occur when SCLK is high, there is thus no possibility that no unitis driving the SCLK line for a short moment when one unit is turning offand the other is turning on. Advantageously, the external circuitrycomprises a pull-up resistor R1 being arranged between a system highvoltage Vcc and the system SCLK.

The means for providing error detection and the methods for obtainingappropriate fault management routines can be implemented in a variety ofways.

The logic sections MS of each unit comprises functionality to notifyother units about whether the given unit is connected (or possiblysuffers a fail state) to the I-CLK and the S-CLK line or not. Each logicunit moreover comprises functionality to learn about which other unitsare connected. Advantageously, a priority scheme is negotiated everytime there is a change in the units being connected, involving that apriority scheme according to which a predetermined order for dedicatingunits is determined. Thereby, all units agree on a subsequent master isbeing dedicated in case another master suffers a fail state. Thepriority scheme could for instance be arranged according to the order atwhich modules are connected. A random order could also be envisioned.The logic sections constitute an autonomous control of the clock systemdisregarding the actual number of clock units being present. No superioror additional clock circuitry is needed.

FIG. 4 shows a preferred embodiment of fault sense circuitry in thefirst unit shown in FIG. 1. For clarity, some of the lines and signalsshown in FIG. 1 have been omitted from being represented on the FIG. 4,although they do exist in this embodiment. The operation of clock sourceCLK1 is provided with error status line SCLK1 that can be checked by thelogic section MS1 reading the state of SCLK1. Likewise, the error statusof bi-directional port BD11 is read over SBD11, the error status ofbi-directional port BD12 is read over SBD12 and the error status of PLLdevice P1 is read over SP1.

When there is a transition on one of these inputs, it will beinterpreted as an asynchronous switch command and will be treated in thesame manner as a switch ordered by an operator. Another possibility isthat a CPU (not shown) associated with the additional functionality ofthe board has a watchdog circuit. If the watchdog timer expires, aswitchover command is generated.

It appears that if CLK1 or BD11 fails, switchover will not effect thesystem clock at all, disregarding whether unit 1 is master or slave.

If the PLL device P1 fails or the bidirectional port BD12 fails whenunit 1 is master, a glitch will appear in the SCLK signal. Hence, in apreferred embodiment of the invention, the reliability of PLL devicesand the bi-directional unit coupled to the output of the PLL device isof a high standard.

It should be noted that, the above mentioned type of faults wouldnormally occur seldom in relation to other faults typically occurring ina system making use of the clock units. In typical applications, theadditional functionality could be based on very large numbers ofcomponents. Hence, in those cases, on average an error is not likely tooccur in the PLL devices or the bidirectional ports connected to theoutputs of the PLL devices, but in some other component. This type offault will be remedied by a hot swap of the module with the faultycomponent. The present invention provides for a seamless switch of unitsin those cases.

It should moreover be noted that alternative embodiments could beenvisioned in which the master unit is not necessarily outputting theclock source on the internal clock line while controlling the systemclock line at the same time. In principle, a given unit could be masterfor the system clock, while another unit could be master for theinternal clock line. The logic circuitry could effectuate that in casemore than two units are prevalent, a mastership for the system clockline is dedicated to a first unit while the mastership for the internalclock line is dedicated to another units.

1-10. (canceled)
 11. A computer system clocking system, said systemcomprising: at least two units with clock functionality, the units beingcoupled to a common system clock line, a common internal clock line, anda logic bus, wherein one unit is dedicated as a master unit at a time,the dedication of the master unit being dependent on at least a signalbeing given so as not to select a given unit for being a master unit,and if a given unit is dedicated as master unit when such a signal isgiven, the system performing a switchover causing another unit as theone not selected to be dedicated as master unit, each unit comprising: aclock source for generating a clock source signal, the clock sourcesignal being adapted for being output on the internal clock line; and aphase lock loop device generating a signal, which is derived from thesignal on the internal clock line, and which is output on the systemclock line if the unit is dedicated as master unit, wherein one sourceclock signal of a unit is output on the internal clock line and allphase lock loop devices of all units generate phase lock loop outputsignals derived from the internal clock signal, the outputs of the phaselock loop devices being in phase with one another such that switchoverfrom one phase lock loop output signal to another is seamless.
 12. Thesystem according to claim 11, wherein the unit dedicated as master unitgenerates the clock source signal on the internal clock line.
 13. Thesystem according to claim 11, wherein each unit further comprises: alogic section communicating with the logic bus; a first bidirectionalport communicating with the internal clock line; a second bidirectionalport communicating with a system clock line, the logic section of theunit controlling the first and second bidirectional ports to input oroutput respective system clock signals and respective internal clocksignals via enable signals.
 14. The system according to claim 13,wherein the enable signals first change state when the system clock isin a logic state with a certain predetermined security time intervalfrom state changes of the system clock.
 15. The system according toclaim 13, wherein the logic section, in cooperation with other logicsections of other units, negotiates a priority scheme according to whicha predetermined order for dedicating units is determined.
 16. The systemaccording to claim 11, wherein the logic section of any unit comprisesfault sense circuitry and wherein, if a fault is detected in any device,the system initiates switchover from a dedicated unit to a subsequentdedicated unit.
 17. The system according to claim 11, comprising anadditional board not comprising any clock generating or clock evaluatingfunctionality, the additional board being coupled to the system clockline but not to the internal clock line nor to the logic bus.
 18. Acomputer system clocking unit comprising: a logic section communicatingwith a logic bus; a clock source for generating a clock source signal,the clock source signal being adapted for being output on an internalclock line; a phase lock loop device having a predeterminedcharacteristic and generating a signal, which is derived from a signalon an internal clock line; first means for outputting the clock sourcesignal to the internal clock line or inputting the internal clock signalfrom the internal clock line; and second means for outputting the signalfrom the phase lock loop device to a system clock line or inputting thesystem clock signal; wherein the logic section of the unit controls thefirst and second means to input or output respective system clocksignals and respective internal clock signals and wherein, if the unitis dedicated as master unit, the logic section controls the phase lockloop generated signal derived from the internal clock signal to beoutput on the system clock line.
 19. The computer system clocking unitaccording to claim 18, wherein if the unit is dedicated as master unit,the logic section controls the source clock signal to be output on theinternal clock line.
 20. The computer system clocking unit according toclaim 18, wherein if the unit is not dedicated as master unit, the logicsection controls the second means to input the system clock signal fromthe system clock line.